LinkedIn Learning FPGA Development\01.Introduction\01.01.Get your digital design journey started.mp4
[f7b86b8e0c2a4c3c]
|
8,970,839 |
D9EF4D1F |
LinkedIn Learning FPGA Development\01.Introduction\01.01.Get your digital design journey started.srt |
2,075 |
4825B29B |
LinkedIn Learning FPGA Development\01.Introduction\01.02.What you should know.mp4
[8a8ecad99050e2f3]
|
2,441,899 |
0C3D5FB0 |
LinkedIn Learning FPGA Development\01.Introduction\01.02.What you should know.srt |
2,106 |
D38787B8 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.03.What is an FPGA.mp4
[d6c2601dd17d7dc9]
|
2,438,147 |
04ED0AE3 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.03.What is an FPGA.srt |
1,555 |
DF83B972 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.04.FPGAs are not microcontrollers.mp4
[65d21894bb2d4b91]
|
1,963,356 |
C1342768 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.04.FPGAs are not microcontrollers.srt |
1,341 |
698E79B8 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.05.FPGA applications and market.mp4
[42514c7cf9833147]
|
2,237,270 |
810759EB |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.05.FPGA applications and market.srt |
1,443 |
9587BC3E |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.06.Inside an FPGA Logic blocks.mp4
[b3d157030162ed18]
|
7,588,871 |
9E16AD5F |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.06.Inside an FPGA Logic blocks.srt |
4,747 |
348C8344 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.07.Inside an FPGA Interconnects.mp4
[9c4647112962511e]
|
3,422,048 |
616BDFDC |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.07.Inside an FPGA Interconnects.srt |
2,697 |
0497F6D9 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.08.Other blocks.mp4
[d2ae4ed3e470cb48]
|
7,777,456 |
027D198C |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays\02.08.Other blocks.srt |
4,468 |
9DF61707 |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.09.FPGA development process overview.mp4
[401cff7387c610ce]
|
9,823,917 |
E1E0EE42 |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.09.FPGA development process overview.srt |
6,859 |
BEE5B6A3 |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.10.FPGA families and development boards.mp4
[9c3d0e760f8ea11e]
|
8,238,084 |
BE961567 |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.10.FPGA families and development boards.srt |
2,647 |
8DCB852D |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.11.Electronic design automation tools.mp4
[15d44ff563fe80ee]
|
3,778,396 |
24C3A554 |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.11.Electronic design automation tools.srt |
2,042 |
66FF190C |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.12.Xilinx platform.mp4
[7794d7c67d36307d]
|
2,229,252 |
AF2E03FA |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.12.Xilinx platform.srt |
1,198 |
7EC5F97A |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.13.Intel platform.mp4
[b5840f0e7040625e]
|
1,969,156 |
DBF1DAEC |
LinkedIn Learning FPGA Development\03.Embedded Development Process\03.13.Intel platform.srt |
1,039 |
B6F77F2A |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.14.Digital system modeling.mp4
[dcd0b03eec7699de]
|
6,608,726 |
6DE4D5CF |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.14.Digital system modeling.srt |
5,608 |
CF30C0BD |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.15.Verilog and VHDL.mp4
[915a851b8a033352]
|
7,123,288 |
346315CA |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.15.Verilog and VHDL.srt |
5,047 |
6D0C0533 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.16.Verilog primer.mp4
[cfe9fc08111d475c]
|
8,830,751 |
A5AC9243 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.16.Verilog primer.srt |
6,556 |
8382D599 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.17.Simulation.mp4
[d2904ce0883b4b96]
|
2,932,229 |
D793A5C1 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.17.Simulation.srt |
2,201 |
947DE1BD |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.18.Combinational logic example.mp4
[68dea46746efa5aa]
|
2,474,668 |
5C9BB6EF |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.18.Combinational logic example.srt |
1,870 |
10585CFA |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.19.4-bit adder simulation example.mp4
[2fb7524e3cb670e7]
|
13,067,094 |
617CA62D |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.19.4-bit adder simulation example.srt |
6,882 |
E90A7FB1 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.20.Sequential logic simulation example.mp4
[e6baf2ac3a1bc38b]
|
12,332,209 |
C51DFCA6 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages\04.20.Sequential logic simulation example.srt |
7,075 |
A694BC9F |
LinkedIn Learning FPGA Development\05.Implementation\05.21.FPGA example implementation requirements.mp4
[db4ba171091d822b]
|
3,164,848 |
18B5A3D6 |
LinkedIn Learning FPGA Development\05.Implementation\05.21.FPGA example implementation requirements.srt |
1,926 |
13C63D07 |
LinkedIn Learning FPGA Development\05.Implementation\05.22.Demo system for the Intel platform.mp4
[729b521393655b28]
|
4,437,336 |
0DB4C342 |
LinkedIn Learning FPGA Development\05.Implementation\05.22.Demo system for the Intel platform.srt |
1,899 |
68112305 |
LinkedIn Learning FPGA Development\05.Implementation\05.23.Intel implementation demo.mp4
[80ea125b34c3cb9c]
|
13,858,140 |
0467C167 |
LinkedIn Learning FPGA Development\05.Implementation\05.23.Intel implementation demo.srt |
5,480 |
5E1EF1F1 |
LinkedIn Learning FPGA Development\05.Implementation\05.24.Intel hardware demo.mp4
[11c4d0e2aa9d4d13]
|
12,259,502 |
0E69039F |
LinkedIn Learning FPGA Development\05.Implementation\05.24.Intel hardware demo.srt |
2,423 |
D087083A |
LinkedIn Learning FPGA Development\05.Implementation\05.25.Demo system for the Xilinx platform.mp4
[eb24d1507b797eb3]
|
4,978,518 |
8A351756 |
LinkedIn Learning FPGA Development\05.Implementation\05.25.Demo system for the Xilinx platform.srt |
3,286 |
514B5BB6 |
LinkedIn Learning FPGA Development\05.Implementation\05.26.Xilinx implementation demo.mp4
[74bb88dc073c4308]
|
21,993,307 |
D5827C2B |
LinkedIn Learning FPGA Development\05.Implementation\05.26.Xilinx implementation demo.srt |
10,029 |
ABE770DD |
LinkedIn Learning FPGA Development\05.Implementation\05.27.Xilinx hardware demo.mp4
[3c34dbc882492257]
|
22,629,892 |
C42F6412 |
LinkedIn Learning FPGA Development\05.Implementation\05.27.Xilinx hardware demo.srt |
4,872 |
8A50E971 |
LinkedIn Learning FPGA Development\06.Conclusion\06.28.Next steps.mp4
[7127fea3c9df1907]
|
2,144,433 |
8C426890 |
LinkedIn Learning FPGA Development\06.Conclusion\06.28.Next steps.srt |
1,212 |
BB079465 |
LinkedIn Learning FPGA Development\Ex_Files_FPGA_Development.zip |
5,625,931 |
262348B6 |
LinkedIn Learning FPGA Development\01.Introduction |
0 |
00000000 |
LinkedIn Learning FPGA Development\02.Field Programmable Gate Arrays |
0 |
00000000 |
LinkedIn Learning FPGA Development\03.Embedded Development Process |
0 |
00000000 |
LinkedIn Learning FPGA Development\04.Hardware Description Languages |
0 |
00000000 |
LinkedIn Learning FPGA Development\05.Implementation |
0 |
00000000 |
LinkedIn Learning FPGA Development\06.Conclusion |
0 |
00000000 |
LinkedIn Learning FPGA Development |
0 |
00000000 |
|
Total size: |
207,440,146 |
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